Field of the Invention
The present invention relates to an analog-to-digital converter, and particularly to a cyclic-type analog-to-digital converter that is useful when used in a probe for medical diagnosis and a medical diagnosis system provided with a probe for medical diagnosis.
Background Art
As diagnosis apparatuses that configure a medical diagnosis system, an ultrasonic diagnosis apparatus and an X-ray CT scanner apparatus are exemplified, for example. Many of these diagnosis apparatuses are used with a probe for medical diagnosis (including a movable-type detection unit in a case of the X-ray CT scanner or the like) that is made to abut on a human body and configure a medical diagnosis system. In relation to the medical diagnosis system, higher resolution of an image inside the human body has been required for further precise diagnosis. A signal measured by a probe for diagnosis is an analog signal, and processing inside the diagnosis apparatus is performed by using a digital signal. Therefore, the medical diagnosis system is provided with an analog-to-digital converter.
With the requirement for the higher resolution of the image inside the body, the medical diagnosis system is required to include a larger number of analog-to-digital converters with higher performances. For example, the medical diagnosis system is required to include multiple high-performance analog-to-digital converters with high resolution that is as high as ten and several bits or greater at a high conversion rate of several tens of Msps or greater. In a case of providing such high-performance analog-to-digital converters in the probe for medical diagnosis, the high-performance analog-to-digital converters are required to have a significantly small occupation area and significantly low power consumption on whole different scales as compared with those in the related art from the viewpoint of a decrease in the size of the probe for medical diagnosis. That is, as the analog-to-digital converters to be mounted to the probe for medical diagnosis, high-performance analog-to-digital converters that have a small occupation area, low power consumption, and high resolution of ten and several bits or greater at a high conversion rate of several tens of Msps or greater are required.
As an analog-to-digital converter that has a small occupation area, in other words, an analog-to-digital converter that is suitable for installation in a small area, a cyclic-type analog-to-digital converter is known. The cyclic-type analog-to-digital converter is disclosed in M. Kim. P. Hanumolu and U. Moon, “A10 MS/s 11-bit 0.19 mm2 algorithmic ADC with improved clocking scheme”, IEEE Journal of Solid-State Circuits, Vol. 44, pp. 2348-2355, September 2009.
Here, a description will be given of a configuration and operations of the cyclic-type analog-to-digital converter. FIGS. 9A to 9D and 10 are diagrams that the present inventors created to review a cyclic-type analog-to-digital converter 900 prior to the present invention.
FIG. 9A is a block diagram illustrating a configuration of the cyclic-type analog-to-digital converter 900 that is configured of a single multiplying digital-to-analog converter circuit (hereinafter, also abbreviated as an MDAC). FIG. 9B is a timing diagram illustrating a conversion operation performed by the MDAC 901 illustrated in FIG. 9A. FIG. 9C is a diagram illustrating a configuration of a cyclic-type analog-to-digital converter 900 that is configured of two MDAC by connecting two MDACs 901a and 901b in series. FIG. 9D is a timing diagram illustrating a conversion operation performed by the two MDACs 901a and 901b illustrated in FIG. 9C. Though not particularly limited, the MDACs 901, 901a, and 901b have the same configuration, and an example of the configuration is illustrated in FIG. 10.
In FIG. 9A, the cyclic-type analog-to-digital converter 900 is provided with the MDAC 901 and a switch 904. First, the switch 904 is arranged on the lower side, and a conductive state is established between a node 904a and a node 904c of the switch 904. In doing so, an input signal 902 as an analog signal is supplied to the MDAC 901. When the switch 904 is arranged on the lower side, the supplied input signal is converted from 4-bit digital signals D1 to D4 in this example. In the 4-bit digital conversion, the MDAC 901 converts each bit of the input signal in a time-series manner from an upper-order bit side (D1, for example) to the lower-order bit side (D4, for example) of the digital signal.
That is, the MDAC 901 samples the supplied input signal, obtains a digital value of 1 bit (D1, for example) corresponding to the sampled voltage value, and outputs the digital value. Then, a residual error (difference) between a voltage corresponding to the obtained digital value of 1 bit (D1, for example) and an input voltage obtained by the sampling is obtained and amplified, and a residual error voltage obtained by the amplification is supplied to the node 904b of the switch 904 via a route 903. The switch 904 is arranged on the upper side so as to establish conduction between the node 904b and the node 904c during a period when the analog-to-digital conversion operation is performed. In doing so, the amplified residual error voltage is input to the MDAC 901 again, and the sampling and the amplification operation are performed. During the sampling, a next bit (D2, for example) is obtained and output. As described above, the analog signal is converted into 4-bit digital signals. Here, each of D1 to D4 is a binary value of ±1 or a ternary value of ±1 and 0.
In FIGS. 9B, 1S, 2S, 3S, and 4S each represent a period (sampling period) during which the sampling is performed by the MDAC 901, and 1A, 2A, 3A, and 4A each represent a period (residual error amplification period) during which the residual error is amplified. Although not particularly limited, the sampling period is substantially the same as the residual error amplification period. Since the analog signal is converted into 4-bit digital signals in this example, one conversion cycle is from the sampling period 1S to the residual error amplification period 4A as illustrated in FIG. 9B. When the analog signal is converted into the digital signal in the time series manner, the conversion cycle is repeated.
FIG. 9C illustrates another configuration of the cyclic-type analog-to-digital converter 900. In the drawing, 901a and 901b each represent an MDAC that has the same configuration as that of the MDAC 901 illustrated in FIG. 9A. However, the MDAC 901a (901b) is different from the MDAC 901 in that the MDAC 901a (901b) converts an input signal into 2-bit digital signals D1 and D3 (D2, D4). In addition, an output of the MDAC 901a is connected to an input of the MDAC 901b via a route 906, and an output of the MDAC 901b is connected to the node 904b of the switch 904 via a route 905. That is, the MDACs 901a and 901b are connected in series and have a two-stage configuration.
The MDAC 901a and the MDAC 901b operate in a mutually overlapping manner. That is, the sampling periods (1S, 3S) of the MDAC 901a overlap the residual error amplification periods (4A, 2A) of the MDAC 901b, and the residual error amplification periods (1A, 3A) of the MDAC 901a overlap the sampling periods (2S, 4S) of the MDAC 901b as illustrated in FIG. 9D. In doing so, it is possible to shorten the conversion cycle of each of the MDACs 901a and 901b into half of the conversion cycle as illustrated in FIG. 9B. In such a case, 2-bit digital signals (D1, D3) are output from the MDAC 901a in the sampling periods 1S and 3S, and 2-bit digital signals (D2, D4) are output from the MDAC 901b in the sampling periods 2S and 4S. As a result, it is possible to shorten the conversion cycle while keeping the same conversion bit number as that of the cyclic-type analog-to-digital converter illustrated in FIG. 9A. That is, it is possible to double the conversion rate. However, since the two MDACs are used, it is considered that an installation area (occupation area) increases.
In order to realize a higher conversion rate in the cyclic-type analog-to-digital converters illustrated in FIGS. 9A and 9C, it is necessary to shorten a time of conversion processing of each bit, which is performed by the MDACs 901, 901a, and 901b. 
Next, a description will be given of the multiplying digital-to-analog converter circuit (MDAC) 901 that was reviewed by the present inventors, with reference to FIG. 10.
The MDAC 901 is basically configured of an analog circuit and includes a rough quantizer 1000 that roughly quantizes an input signal Vin, a digital-to-analog conversion unit (DAC) 1001, a differentiator 1002, and an amplification unit 1003. Here, the input signal Vin is a signal that is supplied to the MDAC 901 via the switch 904 in FIG. 9A or 9C. In addition, an output Vout of the amplification unit 1003 is a signal that is supplied to the route 903, 905, or 906 in FIG. 9A or 9C.
The input voltage Vin is roughly quantized by the rough quantizer 1000, and the result thereof corresponds to the digital signal Di (i-th bit) as an output of the MDAC 900. In addition, the digital signal Di is converted again into an analog voltage corresponding to the digital signal Di by the digital-to-analog conversion unit 1001. A difference from the analog voltage obtained after the conversion and the input voltage Vin is obtained by the differentiator 1002. Since the difference corresponds to a voltage obtained by subtracting the voltage corresponding to the digital signal Di from the input voltage Vin, the difference is regarded as a residual error voltage. The residual error voltage is amplified by the amplification unit 1003 with a gain G, and the output Vout of the MDAC is obtained. The output Vout is used as the next input voltage Vin for the MDAC 901, and conversion processing for obtaining the next bit is performed. By repeating such an operation (MDAC operation) N times, N-bit digital signals D1 to DN are finally obtained. In the example illustrated in FIG. 9A, the MDAC operation (conversion processing) is executed four times.
At this time, a relationship between the analog voltage Vin as the input signal and the digital signals D1 to DN is represented by Equation (1). Here, Q is a quantization error that is caused by the rough quantizer 1000, Gi is a gain of the amplification unit 1003 at the i-th (i=1 to N−1) MDAC, and Vref is a reference voltage. In the case in which a plurality of MDACs 901a and 901b are connected in series as illustrated in FIG. 9C, it is assumed that the gain G of the amplification unit 1003 at each of the MDACs varies between the MDACs. Therefore, the gains of the respective MDACs are separately represented in Equation (1). It is a matter of course that in a case in which the cyclic-type analog-to-digital converter 900 is configured of the single MDAC 901 as in FIG. 9A, each of the gains G1 to GN-1 in Equation (1) may be the gain G of the amplification unit 1003 of the MDAC 901.
                    Vin        =                                            1              2                        ⁢                                          D                1                            ·              Vref                                +                                    1                              2                ⁢                                  G                  1                                                      ⁢                                          D                2                            ·              Vref                                +                                          ⁢                      …            ⁢                                                  ⁢                                          1                                  2                  ⁢                                                            G                      1                                        ·                                          G                      2                                                        ⁢                                                                          ⁢                  …                  ⁢                                                                          ⁢                                                            G                                              N                        -                        2                                                              ·                                          G                                              N                        -                        1                                                                                                        ·                              D                N                            ·              Vref                                +                      Q                                                            G                  1                                ·                                  G                  2                                            ⁢                                                          ⁢              …              ⁢                                                          ⁢                                                G                                      N                    -                    2                                                  ·                                  G                                      N                    -                    1                                                                                                          (        1        )            
Here, a term from which the last term (Q/G1·G2 . . . GN-2·GN-1) of the Equation (1) corresponds to the analog-to-digital conversion result. That is, the term portion from which the last term is removed represents the relationship between the input voltage Vin and the digital signals D1 to DN. In this case, the last term corresponds to a conversion error. Therefore, according to the cyclic-type analog-to-digital converter, it is possible to reduce the conversion error by increasing the gain G (in other words, the residual error amplification rate) of the amplification unit 1003 that is provided in the MDAC to be greater than one and increasing the number N of times of the conversion.
“A10 MS/s 11-bit 0.19 mm2 algorithmic ADC with improved clocking scheme”, discloses the cyclic-type analog-to-digital converter using the MDAC. In the MDAC disclosed in “A10 MS/s 11-bit 0.19 mm2 algorithmic ADC with improved clocking scheme”, the amplification of the residual error is realized by a feedback operation of an operational amplifier. In order to increase the conversion rate of the cyclic-type analog-to-digital converter, it is necessary to shorten the time of the conversion processing of each bit as described above. In order to shorten the time of conversion processing, the use of a wide-band operational amplifier as the operational amplifier is required, and power consumption by the operational amplifier is considered to increase according to “A10 MS/s 11-bit 0.19 mm2 algorithmic ADC with improved clocking scheme”. That is, in a case of increasing the conversion rate, the power consumption by the cyclic-type analog-to-digital converter is considered to increase.
Imran Ahmed, Jan Mulder, David A, Johns, “A 50 MS/s 9.9 mW Pipelined ADC With 58 dB SNDR in 0.18 um CMOS Using Capacitive Charge-Pumps”, 2009 IEEE International Solid-State Circuits Conference, pp. 164-165, February 2009 discloses a pipeline-type analog-to-digital converter. “A 50 MS/s 9.9 mW Pipelined ADC With 58 dB SNDR in 0.18 um CMOS Using Capacitive Charge-Pumps” discloses a technology of realizing residual error amplification without using the operational amplifier. In order to review the technology described therein, the present inventors created a diagram of a circuit as a target of review based on the content disclosed therein. FIG. 11 is an explanatory diagram illustrating a configuration of the circuit as the target of review, which was created by the present inventors. Next, a description will be given of the circuit as the target of review.
The circuit as the target of review that is illustrated in FIG. 11 is provided with capacitance elements C11 and C12, a switch 1101, and a rough quantizer 1100. The operation of the circuit as the target of review can be divided into a sampling period (the left side of the arrow in FIG. 11) and a residual error amplification period (right side of the arrow in FIG. 11) in the same manner as the MDAC 901 illustrated in FIGS. 9A and 9B. That is, the circuit as the target of review operates in the sampling period and then operates in the residual error amplification period. In addition, as input signals Vin, a normal phase input signal +Vin corresponding to the input signal and an opposite phase input signal −Vin with an opposite (inverted) phase with respect to the normal phase input signal Vin are supplied.
In the sampling period, the normal phase input signal +Vin is supplied to one electrode of the capacitance element C11, and the opposite phase input signal −Vin is supplied to the other electrode of the capacitance element C12. In the drawing, the normal phase input signal +Vin and the opposite phase input signal −Vin are depicted as a sine wave and an inverted sine wave in order to expressly illustrate that the normal phase input signal +Vin and the opposite phase input signal −Vin have inverted phases. However, the input signal supplied to one electrode of each of the capacitance elements C11 and C12 in the sampling period is a signal (voltage) at a timing t1 in FIG. 11, for example. At the timing t1, the other electrode of each of the capacitance elements C11 and C12 is connected to an AC ground (ground voltage Vs). That is, a so-called pseudo differential is configured in the sampling period. In doing so, the normal phase input signal +Vin is applied to the AC ground (Vs) between a pair of electrodes of the capacitance element C11, and charging of electric charge is performed in the sampling period. Similarly, the opposite phase input signal −Vin is applied to the AC ground (Vs) between a pair of electrodes of the capacitance element C12, and charging of electric charge is performed.
In addition, the rough quantizer 1100 quantizes the input signal Vin in the sampling period. In FIG. 11, the quantization is performed by dividing a voltage range of the input signal into three stages and determining which of the ranges the voltage of the input signal is present in by the rough quantizer 1100. Here, the digital signal Di that represents one of 0, +1 and −1 is output from the rough quantizer 1100 depending on the voltage value of the input signal.
Next, in the residual error amplification period, one electrode of the capacitance element C12 is connected to the other electrode of the capacitance element C11, and the other electrode of the capacitance element C12 is connected to the switch 1101. In addition, the output signal Vout is extracted from one electrode of the capacitance element C11. The switch 1101 includes three switches 1102 to 1104, and the three switches 1102 to 1104 are brought into an ON state in accordance with the value of the digital signal Di. In doing so, one of reference voltages Vref, 0 V, and −Vref is applied to the other electrode of the capacitance element C12 in accordance with the value of the digital signal Di.
In the residual error amplification period, the capacitance elements C11 and C12 that are electrically charged in the sampling period are connected in series. Therefore, a voltage value of the output signal Vout for the other electrode of the capacitance element C12 is double that of the input signal Vin in accordance with a principle of conversion of charge. In addition, since a voltage (+Vref, 0 v, −Vref) in accordance with the value of the digital signal Di is applied to the other electrode of the capacitance element C12, the output signal Vout becomes a value (residual error) that reflects the value of the digital signal Di after conversion. By performing such a series of operations (the operation in the sampling period and the operation in the residual error amplification period), it is possible to provide the same function as that of the residual error amplification in the MDAC. In a case in which capacitance values of the capacitance elements C11 and C12 are the same capacitance value C, a rate G of residual error amplification is substantially doubled.
According to the circuit as the target of review, it is possible to configure the MDAC without using any operational amplifier. However, it is necessary to provide capacitance elements with capacitance values, a total of which is 2C, and it is considered that the occupation area increases. In addition, since it is necessary to generate three types of reference voltages, namely +Vref, 0 V, and −Vref, it is considered that power consumption increases due to a reference voltage generation circuit that generates these reference voltages and power consumption as a whole increases.